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SIP12110 www.vishay.com vishay siliconix s14-1891-rev. a, 15-sep-14 1 document number: 64299 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 6 a, 4.5 v to 15 v input synchronous buck regulator description the SIP12110 is a high frequency current-mode constant on-time (cm-cot) synchronous buck regulator with integrated high-side and lo w-side power mosfets. its power stage is capable of supplying 6 a continuous current at 1.0 mhz switching frequency. this regulator produces an adjustable output voltage down to 0.6 v from 4.5 v to 15 v input rail to accommodate a variety of applications, including computing, consumer electronics, telecom, and industrial. SIP12110s cm-cot architecture delivers ultrafast transient response with minimum output capacitance and tight ripple regulation at very light load. the part is stable with any capacitor type and no esr network is required for loop stability. the device also incorporates a power saving scheme that significantly increases light load efficiency. the regulator integrates a full protection feature set, including output overvoltage protection (ovp), output under voltage protection (uvp) and thermal shutdown (otp). it also has uvlo for input rail and internal soft-start ramp. the SIP12110 is available in lead (pb)-free power enhanced 3 mm x 3 mm qfn-16 package. features ? 4.5 v to 15 v input voltage ? adjustable output voltage down to 0.6 v ? 6 a continuous output current ? selectable switching frequency from 400 khz to 1.0 mhz with an external resistor ? 95 % peak efficiency ? stable with any capacitor. no external esr network required ? ultrafast transient response ? power saving scheme for increased light load efficiency ? 1 % accuracy of v out setting ? cycle-by-cycle current limit ? fully protected with otp, scp, uvp, ovp ?p good indicator ? -40 c to +125 c operating junction temperature ? output voltage tracking ? material categorization: fo r definitions of compliance please see www.vishay.com/doc?99912 applications ? point of load regulation for low-power processors, network processors, dsps, fpgas, and asics ? low voltage, distributed po wer architectures with 5 v or 12 v rails ? computing, broadband, networking, lan / wan, optical, test and measurement ? a/v, high density cards, storage, dsl, stb, dvr, dtv, industrial pc typical application circuit fig. 1 - typical application circuit for SIP12110 v in p g ood en v cc lx p g nd a g nd power good enable v out v fb comp r on boot input = 4.5 v to 15 v ss
SIP12110 www.vishay.com vishay siliconix s14-1891-rev. a, 15-sep-14 2 document number: 64299 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 marking stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those in dicated in the operational sectio ns of the specifications is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. ordering information part number package marking (line 2: p/n) SIP12110dmp-t1-ge4 qfn16 3x3 2110 SIP12110db reference board absolute maximum ratings electrical parameter conditions limit unit v in reference to p gnd -0.3 to +16 v v cc reference to a gnd -0.3 to +6 lx reference to p gnd -1 to +16 lx (ac voltage) 100 ns; reference to p gnd -2 to +17 10 ns; reference to p gnd -6 to +17 boot -0.3 to v in + v cc a gnd to p gnd -0.3 to +0.3 all logic inputs and outputs (r on , comp, v fb , ss, en, p good ) reference to a gnd -0.3 to v cc +0.3 temperature max. operating junction temperature -40 to +150 c storage temperature -65 to +150 power dissipation junction to ambien t thermal impedance (r thja ) 36.3 c/w maximum power dissipation ambient temperature = 25 c 3.4 w ambient temperature = 100 c 1.3 esd protection electrostatic discharge protection human body model, jesd22-a114 2 kv format: line 1: dot line 2: p/n line 3: s iliconix logo + e s d s ymbol line 4: factory code + year code + work week code + lot code p/n fywll
SIP12110 www.vishay.com vishay siliconix s14-1891-rev. a, 15-sep-14 3 document number: 64299 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note (1) tie v cc to v in when v in < 5.5 v. recommended operating range (all voltages referenced to gnd = 0 v) electrical parameter mi nimum typical maximum unit v in 4.5 - 15 v v cc 4.5 - 5.5 v out 0.6 - 5.5 temperature recommended ambient te mperature -40 to 85 c operating junction temperature -40 to 125 electrical specifications (test condition unless otherwise specified) parameter symbol test condition v in = 12 v, t a = -40 c to 85 c limits unit min. typ. max. power supply power input voltage range v in note 1 4.5 - 15 v v cc regulator voltage v cc 4.555.5 input current iv in_noload t a = 25 c, r on = 75 k , non-switching, i o = 0 a -1.2-ma shutdown current iv in_shdn en = 0 v - 5 8 a v cc uvlo threshold v cc_uvlo v cc rising 2.3 2.55 2.8 v v cc uvlo hysteresis v cc_uvlo_hys - 300 - mv controller and timing feedback reference v fb t a = 25 c 0.596 0.600 0.604 v t a = -40 c to +85 c 0.594 0.600 0.606 v fb input bias current i fb - 2 200 na transconductance g m -1-ms comp source current i comp_source -50- a comp sink current i comp_sink -50- on-time t on r on = 75 k 100 135 170 ns minimum off-time t off_min. 145 200 255 soft start current i ss 357a power mosfets high-side on resistance r on_hs v gs = 5 v -4567 m low-side on resistance r on_ls -2741 fault protections over current limit i ocp inductor valley current - 7.5 - a output ovp threshold v fb_ovp v fb with respect to 0.6 v reference -21- % output uvp threshold v fb_uvp --65- over temperature protection rising temperature - 160 - c hysteresis - 35 - power good power good output threshold v fb_rising_vth_ov v fb rising above 0.6 v reference - 21 - % v fb_falling_vth_uv v fb falling below 0.6 v reference - -12.5 - power good on resistance r on_pgood -3060 power good delay time t dly_pgood -5-s enable threshold logic high level v en_h 1.5 - - v logic low level v en_l --0.4
SIP12110 www.vishay.com vishay siliconix s14-1891-rev. a, 15-sep-14 4 document number: 64299 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 functional block diagram fig. 2 - SIP12110 functi onal block diagram pin configuration fig. 3 - SIP12110 pin configuration (top view) pin configuration pin number name function 1, 16 v in input supply voltage for power mos. v in = 4.5 v to 15 v 2v cc internal regulator output, tie v cc to v in when v in < 5.5 v 3a gnd analog ground 4r on an external resistor between r on and a gnd sets the switching on time. 5 comp connect to an external rc network for loop compensation and droop function. 6v fb feedback voltage. 0.6 v (typ.). use a resistor divider between v out and a gnd to set the output voltage. 7 ss an external capacitor between ss and a gnd sets the soft start time. 8 en enable pin. pull enable above 1.5 v to enable and below 0.4 v to disable the pa rt. do not float this pin. 9p good power good output. open drain. 10, 11, 12 lx switching node, inductor connection point 13 boot bootstrap pin - connect a ca pacitor of at least 100 nf from boot to lx to de velop the floating supply for the high-side gate drive. 14, 15, pad p gnd power ground on-time generator + - pwm comparator s oft s tart 0.6 v reference a g nd p g ood vcc en vfb vin lx p g nd vin vcc anti- xcond control zcd + - 0.72 v ov comparator control logic s ectionl ocp uvlo otp comp ota + - + i s en s e i-v converter i s en s e ron + - 0.45 v vfb uv comparator current mirror 5 v regulator vcc 5 a ss vcc lx lx p g nd boot pad en v in v in v fb ss lx comp p g ood v cc p g nd 1 2 3 4 5 6 7 8 12 11 10 9 15 14 1 3 16 p g nd boot r on a g nd lx p g nd lx
SIP12110 www.vishay.com vishay siliconix s14-1891-rev. a, 15-sep-14 5 document number: 64299 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics (v in = 12 v, v out = 1.2 v, l = 1.5 h, c = 3 x 22 f, unless otherwise noted) fig. 4 - efficiency vs. i out fig. 5 - frequency variation vs. i out fig. 6 - steady-state, i out = 0 a ch1 (brn) = lx (10 v/div), ch3 (blu) = v out (20 mv/div), ch2 (red) = i coil (1 a/div), time = 10 s/div fig. 7 - load regulation vs. i out fig. 8 - en threshold vs. temperature fig. 9 - steady-state, i out = 6 a ch1 (brn) = lx (10 v/div), ch3 (blu) = v out (20 mv/div), ch2 (red) = i coil (1 a/div), time = 1 s/div 20 30 40 50 60 70 80 90 100 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 efficiency (%) i out (a) v out = 1.2 v v out = 5 v 0 200 400 600 800 1000 1200 1400 1600 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 s witching fre q uency, f s w (khz) i out (a) v out = 1.2 v v out = 5 v ch2 ch3 ch1 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 load regulation (%) i out (a) v out = 1.2 v v out = 5 v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 -60 -40 -20 0 20 40 60 80 100 120 140 en thre s hold voltage, v en (v) temperature ( c) v en_l v en _ h ch2 ch3 ch1
SIP12110 www.vishay.com vishay siliconix s14-1891-rev. a, 15-sep-14 6 document number: 64299 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 10 - load step undershoot response, i out = 0 a to 6 a ch3 (blu) = v out (500 mv/div), ch1 (brn) = lx (10 v/ div), time = 20 s/div fig. 11 - load step undershoot response, i out = 0 a to 3 a ch2 (red) = i coil (5 a/div), ch3 (blu) = v out (200 mv/div), ch1 (brn) = lx (10 v/ div), time = 10 s/div fig. 12 - start-up, i out = 0 a ch1 (brn) = lx (10 v/div), ch3 (blu) = v out (0.5 v/div), ch2 (red) = i coil (2 a/div), time = 200 s/div fig. 13 - load step overshoot response, i out = 6 a to 0 a ch3 (blu) = v out (500 mv/div), ch1 (brn) = lx (10 v/ div), time = 20 s/div fig. 14 - load step overshoot response, i out = 3 a to 0 a ch2 (red) = i coil (5 a/div), ch3 (blu) = v out (200 mv/div), ch1 (brn) = lx (10 v/ div), time = 10 s/div fig. 15 - start-up, i out = 6 a ch1 (brn) = lx (10 v/div), ch3 (blu) = v out (0.5 v/div), ch2 (red) = i coil (5 a/div), time = 500 s/div ch1 ch3 ch1 ch3 ch2 ch2 ch1 ch3 ch1 ch3 ch1 ch3 ch2 ch3 ch1 ch2
SIP12110 www.vishay.com vishay siliconix s14-1891-rev. a, 15-sep-14 7 document number: 64299 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 16 - shut-down, i out = 0 a ch1 (brn) = lx (10 v/div), ch3 (blu) = v out (0.5 v/div), ch2 (red) = i coil (2 v/div), time = 5 ms/div fig. 17 - over current protection, i valley = 6 a ch2 (red) = i coil (1 a/div), ch3 (blu) = v out (200 mv/div), ch1 (brn) = lx (10 v/ div), time = 100 s/div fig. 18 - shut-down, i out = 6 a ch1 (brn) = lx (10 v/div), ch3 (blu) = v out (0.5 v/div), ch2 (red) = i coil (5 a/div), time = 200 s/div fig. 19 - over current protection, i valley = 6 a ch2 (red) = i coil (1 a/div), ch3 (blu) = v out (200 mv/div), ch1 (brn) = lx (10 v/ div), time = 10 s/div ch2 ch1 ch3 ch1 ch2 ch3 ch2 ch1 ch3 ch1 ch3 ch2
SIP12110 www.vishay.com vishay siliconix s14-1891-rev. a, 15-sep-14 8 document number: 64299 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 operational description device overview SIP12110 is a high-efficiency monolithic synchronous buck regulator capable of delivering up to 6 a continuous current. the device has progr ammable switching frequency up to 1 mhz. the control scheme is based on current-mode constant-on-time architecture, which delivers fast transient response and minimi zes external compone nts. thanks to the internal current ramp inform ation, no high-esr output bulk or virtual esr network is re quired for the loop stability. this device also incorporates a power saving feature by enabling diode emulation mode and frequency foldback as load decreases. SIP12110 has a full set of protection and monitoring features: - over current protection in pulse-by-pulse mode - output over voltage protection - output under voltage prote ction with device latch - over temperature prote ction with hysteresis - dedicated enable pin for easy power sequencing - power good open drain output this device is available in qfn16 3 x 3 package to deliver high power density an d minimize pcb area. power stage SIP12110 integrates a high-performance power stage with a ~ 45 m high side n-channel mosfet and a ~ 27 m low side n-channel mosfet. the mosfets are optimized to achieve 95 % efficiency at up to 1 mhz switching frequency. the power input voltage (v in ) can go up to 15 v and down as low as 4.5 v for the power conversion. the logic bias voltage (v cc ) ranges from 4.5 v to 5.5 v. pwm control mechanism SIP12110 employs a state-of-the-art current-mode cot control mechanism. during stea dy-state operation, output voltage is compared with intern al reference (0.6 v typ.) and the amplified error signal (v comp ) is generated on the comp pin. in the meantime, inductor valley current is sensed, and its slope (i sense ) is converted into a voltage signal (v current ) to be compared with v comp . once v current is lower than v comp , a single shot on-time is generated for a fixed time programmed by the external r on . figure 20 illustrates the basic block diagram for cm-cot architecture and figure 21 demonstrates the basic operational principle: fig. 20 - cm-cot block diagram fig. 21 - cm-cot operational principle h g l g h g l g ota - + bandgap v ref v out current mirror l s fet pwm comparator - + - + v in i-amp on-time generator 0.8 v v in r on control logic & mo s fet driver v comp i s en s e v current v current v comp pwm fixed on-time
SIP12110 www.vishay.com vishay siliconix s14-1891-rev. a, 15-sep-14 9 document number: 64299 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 the following equation illustra tes the relationship between on-time, v in , v out and r on value: once on-time is set, the pseudo constant frequency is then determined by the following equation: loop stability and compensator design due to the nature of current mode cont rol, a simple rc network (type ii compens ator) is required between comp and a gnd for loop stability and transient response purpose . the general concept of this loop design is to introduce a single zero through th e compensator to determine the crossover frequency of overall close loop system. the overall loop can be broken down into following segments. output feedback divider transfer function h fb z: voltage compensator transfer function g comp (s): modulator transfer function h mod (s): the complete loop transfer function is given by: when: c comp = compensation capacitor r comp = compensation resistor gm = error amplifier transconductance r load = load resistance c o = output capacitor r ds(on) = ls switch resistance r fb1 = feedback resistor connect to lx r fb2 = feedback resistor connect to ground r o = output impedance of error amplifier = 20 m av 1 = voltage to current gain = 3 light load operation to further improve efficiency at light-load condition, SIP12110 provides a set of inno vative implementations to eliminate ls recirculating current and switching losses. the internal zero crossing detect or (zcd) monitors lx node voltage to determine when indu ctor current starts to flow negatively. in light load operation as soon as inductor valley current crosses zero, th e device first deploys diode emulation mode by turning off ls fet. if load further decreases, switching freq uency is further reduced proportional to load condition to save switching losses while keeping output ripple within tolerance. the switching frequency is set by the controlle r to maintain regulation. at zero load this frequency can go as low as hundreds of hz. output monitoring and protection features output over-current protection (ocp) SIP12110 has pulse-by-pulse over-current limit control. the inductor valley current is mo nitored during ls fet turn-on period through r ds(on) sensing. after a pre-defined time, the valley current is compared with internal threshold (7.5 a typ.) to determine the threshold for ocp. if monitored current is higher than threshold, hs tu rn-on pulse is skipped and ls fet is kept on until the valley current returns below ocp limit. in the severe over-current cond ition, pulse-by-pulse current limit eventually triggers ou tput under-voltage protection (uvp), which latches the device off to prevent catastrophic thermal-related failure. uvp is described in the next section. ocp is enabled immediately after v cc passes uvlo level. v in 1 t on = r on x k x , where k = 17.5 x 10 -12 i s a con s tant s et internally f sw d t on ------- v out v in ------------- - 1 v in -------- r on k ------------------------------------ - v out r on k --------------------- == = h fb r fb2 r fb1 x r fb2 ----------------------------- - = g comp (s) r o x 1 + sc comp r comp () 1 + sr o c comp () ------------------------------------------------------------------------- gm = h mod (s) 1 av 1 x r ds(on) ----------------------------------- x r load x 1 + sc o r esr () 1 + sc o r load () ------------------------------------------------------------- - = h mod (s) r fb2 r fb1 x r fb2 ----------------------------- - x r o x 1 + sc comp r comp () 1 + sr o c comp () ------------------------------------------------------------------------- gm x 1 av 1 x r ds(on) ----------------------------------- x r load x 1 + sc o r esr () 1 + sc o r load () ------------------------------------------------------------- - =
SIP12110 www.vishay.com vishay siliconix s14-1891-rev. a, 15-sep-14 10 document number: 64299 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 22 - over-current protection illustration output under-voltag e protection (uvp) uvp is implemented by moni toring output through v fb pin. once the voltage level at v fb is below 0.2 v for more than 20 s, then uvp event is recognized and both hs and ls mosfets are turned off. uvp latches the device off until either v cc or en is recycled. uvp is only active after the completion of soft-start sequence. output over-voltage protection (ovp) for ovp implementation, outp ut is monitored through v fb pin. after soft-start, if the voltage level at v fb is above 21 % (typ.), ovp is triggered with hs fet turning off and ls fet turning on immediatel y to discharge the output. normal operation is resumed once v fb drops back to 0.675 v. ovp is active immediately after v cc passes uvlo level. over-temperature protection (otp) SIP12110 has internal thermal monitor block that turns off both hs and ls fets when j unction temperature is above 160 c (typ.). a hysteresis of 30 c is implemented, so when junction temperatu re drops below 130 c, the device restarts by initiating the soft-start sequence again. soft start up SIP12110 soft-start time is adjustable by selecting a capacitor value from the fo llowing equation. once v cc is above uvlo level (2.55 v typ.), v out will ramp up slowly, rising monotonically to the programmed output voltage. there is an internal 5 a current source tied to the soft start pin which charges the external soft start cap during soft-start period, ocp is activated. ovp and short-circuit protection are not active until soft-start is complete. pre-bias startup in case of pre-bias startup, output is monitored through v fb pin. if the sensed voltage on v fb is higher than the internal reference ra mp value, control logic prevents hs and ls fet from switching to avoid negative output voltage spike and excessive current sinking through ls fet. power good (p good ) SIP12110s power good is an open-drain output. pull p good pin high up to 5 v through a 10k resistor to use this signal. power good window is shown in the below diagram. if voltage level on v fb pin is out of this window, p good signal is de-asserted by pulling down to gnd. fig. 23 - p good window and timing diagram s kipped g h pul s e i load ocp thre s hold i inductor g h ss time cext 0.8 v 5 a --------------------------------- = v ref (0.6 v) v fb v fb _ri s ing_v th _ov (typ. = 0.725 v) v fb _falling_v th _ov (typ. = 0.675 v) v fb _falling_v th _uv (typ. = 0.525 v) v fb _ri s ing_v th _uv (typ. = 0.575 v) p g pull-high pull-low
SIP12110 www.vishay.com vishay siliconix s14-1891-rev. a, 15-sep-14 11 document number: 64299 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 24 - reference board schematic pgd en pgd en vognd vcc vcc ic1 SIP12110 vin1 1 vcc 2 agnd 3 ron 4 gmo 5 vfb 6 ss 7 en 8 pgood 9 lx1 10 lx2 11 lx3 12 boot 13 pgnd1 14 pgnd2 15 vin2 16 pgnd0 17 j3 vo_gnd 1 c5 0.1uf c8 10n c7 2.2u c3 22uf j2 vout 1 c9 0.47nf j6 pgd 1 r3 6.04k j4 vin_gnd 1 r4 100k r7 5k11 l1 1uh r6 5k11 j1 vin 1 c1 0.1uf c4 22uf r2 0 r5 100k c2 22uf c6 0.1uf j5 en 1 r1 75k
SIP12110 www.vishay.com vishay siliconix s14-1891-rev. a, 15-sep-14 12 document number: 64299 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pcb layout of reference board fig. 25 - top layer fig. 26 - inner layer1 fig. 27 - bottom layer fig. 28 - inner layer2 bill of material item qty reference value voltage fo otprint part number manufacturer 1 3 c1, c5, c6 0.1 f 35 v c0402-tdk gmk105bj104kv-f taiyo yuden 2 2 c2, c3 22 f 10 v c0805-tdk lmk212bj226mg-t taiyo yuden 3 1 c4 22 f 35 v c0805-tdk c2012x5r1v226m125ac tdk 4 1 c7 2.2 f 16 v c0603-tdk c0603c225k4pactu kemet 5 1 c8 10 nf 16 v c0402-tdk cc0402krx7r7bb103 yageo 6 1 c9 0.47 nf 50 v c0402-tdk c1005c0g1h471j050ba tdk 7 1 ic1 SIP12110 - qfn16 3 x 3 SIP12110dmp-t1-ge4 vishay 86 j1, j2, j3, j4, j5, j6 v in , v out , v o_gnd , v in_gnd , en, pgd - tp30 2108-2-00-44-00-00-07 mill-max 9 1 l1 1 h - ihlp1616 ihlp1616bzer1r0m11 vishay 10 1 r1 75 k - r0402-vishay crcw040275k0fkedhp vishay 11 1 r2 0 - r0402-vishay rcg04020000z0ed vishay 12 1 r3 6.04 k - r0402-vishay crcw04026k04fked vishay 13 2 r4, r5 100 k - r0402-vishay crcw0402100kfked vishay 14 2 r6, r7 5.11k - r0402-vishay crcw04025k11fked vishay
SIP12110 www.vishay.com vishay siliconix s14-1891-rev. a, 15-sep-14 13 document number: 64299 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 case outline notes (1) use millimeters as the primary measurement. (2) dimensioning and to lerances conform to asme y14.5m. - 1994. (3) n is the number of terminal s. nd and ne is the number of terminals in each d and e site respectively. (4) dimensions b applies to plated terminal and is measured between 0.15 mm and 0.30 mm from terminal tip. (5) the pin 1 identifier must be existed on the top surface of the package by using identification mark or other feature of package body. (6) package warpage max. 0.05 mm. dimension millimeters (1) inches min. nom. max. min. nom. max. a 0.75 0.85 0.95 0.029 0.033 0.037 a1 0 - 0.05 0 - 0.002 a3 0.20 ref. 0.001 ref. b 0.18 0.25 0.30 0.007 0.010 0.012 d 3.00 bsc 0.118 bsc d2 1.5 1.6 1.7 0.059 0.063 0.067 e 0.50 bsc 0.020 bsc e 3.00 bsc 0.118 bsc e2 1.5 1.6 1.7 0.059 0.063 0.067 l 0.3 0.4 0.5 0.012 0.016 0.020 n (3) 16 16 nd (3) 44 ne (3) 44 bottom view top view s ide view (4) terminal tip pin 1 location indentifier (5) pin 1 dot by marking 3 x e e b s eating plane e2 c 5 6 7 8 16 15 14 13 4 3 2 1 9 10 11 12 4 3 2 d d2 d/2 e/2 e l a1 a 1 a3
SIP12110 www.vishay.com vishay siliconix s14-1891-rev. a, 15-sep-14 14 document number: 64299 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 recommended land pattern for qfn16 3 mm x 3 mm vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?64299. dimen s ion s are in millimeter s 0.500 pitch 2 x 1.740 16 x 0.580 16 x 0.300 4 x 0.200 2 x 3.300
pad pattern www.vishay.com vishay siliconix revision: 10-jul-14 1 document number: 65752 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 recommended land pattern qfn16 3x3 all dimen s ion s are in millimeter s
legal disclaimer notice www.vishay.com vishay revision: 08-feb-17 1 document number: 91000 disclaimer ? all product, product specifications and data ar e subject to change with out notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of th e products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product , (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all implied warranties, includ ing warranties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain types of applicatio ns are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular applic ation. it is the customers responsibility to validate tha t a particular product with the prope rties described in the product sp ecification is suitable for use in a particular application. parameters provided in datasheets and / or specifications may vary in different ap plications and perfor mance may vary over time. all operating parameters, including ty pical parameters, must be va lidated for each customer application by the customer s technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product could result in personal injury or death. customers using or selling vishay product s not expressly indicated for use in such applications do so at their own risk. please contact authorized vishay personnel to obtain writ ten terms and conditions rega rding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners. ? 2017 vishay intertechnology, inc. all rights reserved

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